MIPS Dictionary

Your friendly guide to all MIPS assembly keywords! Explore and learn.

Explored: 0 / 750%

add

Arithmetic

Signed add: rd = rs + rt; traps on overflow.

add $t0, $t1, $t2   # $t0 = $t1 + $t2 (overflow traps)

💡

Use addu if you don’t want overflow exceptions.

addu

Arithmetic

Unsigned add: rd = rs + rt; no overflow trap.

addu $t0, $t1, $t2  # $t0 = $t1 + $t2 (no trap)

💡

‘Unsigned’ here means “no trap,” not “modular only for unsigned data.”

sub

Arithmetic

Signed subtract: rd = rs - rt; traps on overflow.

sub $t0, $t1, $t2   # $t0 = $t1 - $t2 (overflow traps)

💡

sub is add with two’s-complement negate of rt under the hood.

subu

Arithmetic

Unsigned subtract: rd = rs - rt; no overflow trap.

subu $t0, $t1, $t2  # $t0 = $t1 - $t2 (no trap)

💡

Matches addu’s “no trap” behavior.

addi

Arithmetic

Signed add immediate: rt = rs + imm; traps on overflow.

addi $t0, $t1, 5    # $t0 = $t1 + 5 (overflow traps)

💡

Use addiu to avoid overflow traps.

addiu

Arithmetic

Add immediate (no trap): rt = rs + imm.

addiu $t0, $t1, -1  # $t0 = $t1 - 1 (no trap)

💡

Despite the ‘u’, it’s commonly used for signed offsets safely.

slt

Comparison

Set on less than (signed): rd = (rs < rt) ? 1 : 0.

slt $t0, $t1, $t2   # $t0 = 1 if $t1 < $t2 (signed)

💡

Backbone for implementing comparisons in MIPS.

sltu

Comparison

Set on less than (unsigned): rd = (rs < rt) ? 1 : 0.

sltu $t0, $t1, $t2  # unsigned comparison

💡

Use for pointers and size_t-like logic.

slti

Comparison

Set on less than immediate (signed).

slti $t0, $t1, 10   # $t0 = 1 if $t1 < 10 (signed)

💡

Pairs with branch-on-true to emulate <=, >=, etc.

sltiu

Comparison

Set on less than immediate (unsigned).

sltiu $t0, $t1, 10  # unsigned compare with 10

💡

Great for bounds checks on indices.

and

Logic

Bitwise AND: rd = rs & rt.

and $t0, $t1, $t2   # mask bits

💡

Classic for clearing bits with a mask.

or

Logic

Bitwise OR: rd = rs | rt.

or $t0, $t1, $t2    # set bits

💡

Combine masks to assemble values.

xor

Logic

Bitwise XOR: rd = rs ^ rt.

xor $t0, $t1, $t2   # toggle bits

💡

Swap trick uses XOR, but be careful with aliasing.

nor

Logic

Bitwise NOR: rd = ~(rs | rt).

nor $t0, $t1, $t2   # bitwise NOT of OR

💡

Used to synthesize NOT: nor $t0, $t1, $zero.

andi

Logic

Bitwise AND immediate: rt = rs & imm (zero-extended).

andi $t0, $t1, 0xFF # keep low byte

💡

Immediate is zero-extended, not sign-extended.

ori

Logic

Bitwise OR immediate: rt = rs | imm (zero-extended).

ori $t0, $t1, 0x20   # set bit 5

💡

Common with LUI to build 32-bit constants.

xori

Logic

Bitwise XOR immediate: rt = rs ^ imm (zero-extended).

xori $t0, $t1, 1     # toggle LSB

💡

XOR with same value twice gets you back the original.

lui

Data Movement

Load upper immediate: rt = imm << 16.

lui $t0, 0x1234     # $t0 = 0x12340000

💡

Usually followed by ORI to form a full 32-bit constant.

sll

Shift

Logical left shift: rd = rt << shamt.

sll $t0, $t1, 2     # multiply by 4

💡

nop is sll $zero, $zero, 0.

srl

Shift

Logical right shift: rd = rt >>> shamt (zeros in).

srl $t0, $t1, 1     # divide by 2 (unsigned)

💡

Use sra for signed arithmetic right shift.

sra

Shift

Arithmetic right shift: rd = rt >> shamt (sign-ext).

sra $t0, $t1, 1     # divide by 2 (signed)

💡

Maintains sign for negative numbers.

sllv

Shift

Variable logical left shift: rd = rt << rs[4:0].

sllv $t0, $t1, $t2  # shift by $t2 amount

💡

Shift amount comes from a register instead of shamt.

srlv

Shift

Variable logical right shift: rd = rt >>> rs[4:0].

srlv $t0, $t1, $t2  # variable shift right (zeros)

💡

Great for bitfield extraction.

srav

Shift

Variable arithmetic right shift: rd = rt >> rs[4:0].

srav $t0, $t1, $t2  # variable signed shift right

💡

Preserves sign across variable shifts.

mult

Multiply/Divide

Signed multiply: HI|LO = rs * rt (low 32 in LO, high 32 in HI).

mult $t1, $t2  
mflo $t0        # $t0 = low 32 bits

💡

Use mfhi/mflo to read the results; operation is 64-bit internally.

multu

Multiply/Divide

Unsigned multiply: HI|LO = rs * rt (unsigned).

multu $t1, $t2 
mfhi $t3        # $t3 = high 32 bits

💡

Unsigned variant for size_t-like math.

div

Multiply/Divide

Signed divide: LO = rs / rt, HI = rs % rt.

div $t1, $t2 
mflo $t0  # quotient
mfhi $t3  # remainder

💡

Division by zero is undefined—don’t do it.

divu

Multiply/Divide

Unsigned divide: LO = rs / rt, HI = rs % rt (unsigned).

divu $t1, $t2 
mflo $t0 
mfhi $t3

💡

Match your data types when choosing div vs divu.

mfhi

HI/LO

Move From HI: rd = HI.

mfhi $t0  # get remainder or high product

💡

Pairs with mult*/div* to harvest high 32 bits.

mflo

HI/LO

Move From LO: rd = LO.

mflo $t0  # get quotient or low product

💡

You typically read LO first after mult/div.

mthi

HI/LO

Move To HI: HI = rs.

mthi $t0  # set HI explicitly

💡

Less common; can seed HI/LO for custom arithmetic.

mtlo

HI/LO

Move To LO: LO = rs.

mtlo $t0  # set LO explicitly

💡

Caution: overwrites results from mult/div.

j

Control Flow

Jump to absolute target in same 256 MB region.

j main    # PC = target

💡

Assembler fills the 26-bit target field.

jal

Control Flow

Jump and link: $ra = return addr; jump to target.

jal func  # call func; $ra = next PC

💡

Your automatic ‘bookmark’ to get home from a call.

jr

Control Flow

Jump register: PC = rs (return or indirect jump).

jr $ra    # return to caller

💡

Commonly used to return from subroutines.

jalr

Control Flow

Jump and link register: rd=$ra (default), PC=rs.

jalr $t0        # call via pointer in $t0

💡

Useful for function pointers / virtual dispatch.

beq

Control Flow

Branch if equal: if (rs == rt) PC += offset.

beq $t0, $t1, loop   # if equal, branch

💡

Offset is word-aligned relative to the delay slot.

bne

Control Flow

Branch if not equal: if (rs != rt) PC += offset.

bne $t0, $t1, loop   # if not equal, branch

💡

Classic for while/for loops.

blez

Control Flow

Branch if less than or equal to zero (signed).

blez $t0, done  # if $t0 <= 0

💡

One-source-operand branch; compares to zero.

bgtz

Control Flow

Branch if greater than zero (signed).

bgtz $t0, loop  # if $t0 > 0

💡

Complements blez/bltz/bgez.

bltz

Control Flow

Branch if less than zero (signed).

bltz $t0, neg   # if $t0 < 0

💡

Implemented via the REGIMM encoding group.

bgez

Control Flow

Branch if greater than or equal to zero (signed).

bgez $t0, nonneg # if $t0 >= 0

💡

Pairs with bltz for signed zero tests.

bltzal

Control Flow

Branch if < 0 and link (like call-if-negative).

bltzal $t0, handler  # if negative, $ra=ret; jump

💡

Useful for conditional calls / trampolines.

bgezal

Control Flow

Branch if >= 0 and link.

bgezal $t0, handler  # if nonnegative, call handler

💡

Dual of bltzal for nonnegative case.

lb

Memory

Load byte (signed): rt = sign_extend(M8[rs + imm]).

lb $t0, 0($t1)   # signed 8-bit load

💡

Sign-extends bit 7 into upper bits.

lbu

Memory

Load byte (unsigned): rt = zero_extend(M8[rs + imm]).

lbu $t0, 0($t1)  # unsigned 8-bit

💡

Great for ASCII/bytes processing.

lh

Memory

Load halfword (signed): rt = sign_extend(M16[rs + imm]).

lh $t0, 0($t1)   # signed 16-bit load (aligned)

💡

Requires halfword alignment on MIPS I.

lhu

Memory

Load halfword (unsigned): rt = zero_extend(M16[rs + imm]).

lhu $t0, 0($t1)  # unsigned 16-bit load

💡

Keeps upper bits zero.

lw

Memory

Load word: rt = M32[rs + imm].

lw $t0, 4($sp)   # load 32-bit word

💡

Requires word alignment on MIPS I.

sb

Memory

Store byte: M8[rs + imm] = rt[7:0].

sb $t0, 0($t1)   # store low byte

💡

Upper 24 bits of rt are ignored.

sh

Memory

Store halfword: M16[rs + imm] = rt[15:0].

sh $t0, 2($t1)   # store 16 bits (aligned)

💡

Requires halfword alignment.

sw

Memory

Store word: M32[rs + imm] = rt.

sw $t0, 8($sp)   # store 32-bit word

💡

Workhorse for saving registers on stack.

lui (as const-build)

Data Movement

First half of building 32-bit constants (upper 16 bits).

lui $t0, 0x1234 
ori $t0, $t0, 0x5678

💡

MIPS lacks a single ‘load 32-bit immediate’ real instruction.

syscall

System

Enter operating system / simulator service routine.

li $v0, 1
li $a0, 42
syscall   # print_int in SPIM/MARS

💡

Meaning depends on $v0 in simulators like MARS/QtSPIM.

break

System

Breakpoint exception for debuggers.

break 0        # trigger BREAK exception

💡

Handy for trapping illegal states while debugging.

move

Pseudoinstruction

Copy register (pseudo): rd = rs.

move $t0, $t1     # expands to addu $t0,$t1,$zero

💡

Just OR/ADDU with $zero under the hood.

li

Pseudoinstruction

Load immediate (pseudo): rt = imm (32-bit).

li $t0, 0x12345678  # expands to LUI/ORI pair

💡

Short immediates may expand to a single addiu/ori.

la

Pseudoinstruction

Load address (pseudo): rt = address(label).

la $t0, array     # builds absolute address

💡

Assembles using LUI/ORI (and possibly relocation).

neg

Pseudoinstruction

Negate (pseudo): rd = -rs.

neg $t0, $t1      # expands to subu $t0,$zero,$t1

💡

Also exists as ‘negu’ pseudo for no-trap form.

not

Pseudoinstruction

Bitwise NOT (pseudo): rd = ~rs.

not $t0, $t1      # expands to nor $t0,$t1,$zero

💡

Uses NOR trick to invert bits.

nop

Pseudoinstruction

No operation (pseudo): does nothing.

nop               # sll $zero,$zero,0

💡

Often used to fill delay slots in older pipelines.

b

Pseudoinstruction

Unconditional branch (pseudo).

b loop            # expands to beq $zero,$zero,loop

💡

Nice for simple gotos/loops.

bal

Pseudoinstruction

Branch and link (pseudo): like jal with PC-relative target.

bal func          # expands via bgezal $zero, func (tool-dependent)

💡

Assembler tricks vary; effect is set $ra and branch.

beqz

Pseudoinstruction

Branch if equal to zero (pseudo).

beqz $t0, done    # beq $t0,$zero,done

💡

Saves you a $zero in the mnemonic.

bnez

Pseudoinstruction

Branch if not equal to zero (pseudo).

bnez $t0, loop    # bne $t0,$zero,loop

💡

Common in while loops.

ble

Pseudoinstruction

Branch if ≤ (pseudo, signed).

ble $t0, $t1, L   # expands via slt/bne patterns

💡

Assembler synthesizes using slt/beq/bne sequences.

bge

Pseudoinstruction

Branch if ≥ (pseudo, signed).

bge $t0, $t1, L   # expands via slt/bne patterns

💡

No native ‘bge’ in MIPS I.

blt

Pseudoinstruction

Branch if < (pseudo, signed).

blt $t0, $t1, L   # expands via slt/bne

💡

Assembled with slt/beq combos.

bgt

Pseudoinstruction

Branch if > (pseudo, signed).

bgt $t0, $t1, L   # expands via slt/bne

💡

Assembler sugar only.

seq

Pseudoinstruction

Set if equal (pseudo): rd = (rs == rt).

seq $t0, $t1, $t2  # expands via xor/sltiu/xori

💡

A convenient booleanizer in MARS/QtSPIM.

sne

Pseudoinstruction

Set if not equal (pseudo): rd = (rs != rt).

sne $t0, $t1, $t2  # expands via seq/xori

💡

Pairs with seq to build conditionals.

sle

Pseudoinstruction

Set if ≤ (pseudo, signed).

sle $t0, $t1, $t2  # pseudo via slt/seq/or

💡

Not a real opcode; assembler composes it.

sge

Pseudoinstruction

Set if ≥ (pseudo, signed).

sge $t0, $t1, $t2  # pseudo via slt/xori

💡

Assembler sugar for comparisons.

rol

Pseudoinstruction

Rotate left (pseudo).

rol $t0, $t1, 8    # pseudo via sll/srl/or

💡

No real rotate in MIPS I—built from shifts.

ror

Pseudoinstruction

Rotate right (pseudo).

ror $t0, $t1, 8    # pseudo via srl/sll/or

💡

Assembler expands with opposite shifts and OR.

MIPS Dictionary

Your friendly guide to all MIPS assembly keywords! Explore and learn.

Explored: 0 / 750%

add

Arithmetic

Signed add: rd = rs + rt; traps on overflow.

add $t0, $t1, $t2   # $t0 = $t1 + $t2 (overflow traps)

💡

Use addu if you don’t want overflow exceptions.

addu

Arithmetic

Unsigned add: rd = rs + rt; no overflow trap.

addu $t0, $t1, $t2  # $t0 = $t1 + $t2 (no trap)

💡

‘Unsigned’ here means “no trap,” not “modular only for unsigned data.”

sub

Arithmetic

Signed subtract: rd = rs - rt; traps on overflow.

sub $t0, $t1, $t2   # $t0 = $t1 - $t2 (overflow traps)

💡

sub is add with two’s-complement negate of rt under the hood.

subu

Arithmetic

Unsigned subtract: rd = rs - rt; no overflow trap.

subu $t0, $t1, $t2  # $t0 = $t1 - $t2 (no trap)

💡

Matches addu’s “no trap” behavior.

addi

Arithmetic

Signed add immediate: rt = rs + imm; traps on overflow.

addi $t0, $t1, 5    # $t0 = $t1 + 5 (overflow traps)

💡

Use addiu to avoid overflow traps.

addiu

Arithmetic

Add immediate (no trap): rt = rs + imm.

addiu $t0, $t1, -1  # $t0 = $t1 - 1 (no trap)

💡

Despite the ‘u’, it’s commonly used for signed offsets safely.

slt

Comparison

Set on less than (signed): rd = (rs < rt) ? 1 : 0.

slt $t0, $t1, $t2   # $t0 = 1 if $t1 < $t2 (signed)

💡

Backbone for implementing comparisons in MIPS.

sltu

Comparison

Set on less than (unsigned): rd = (rs < rt) ? 1 : 0.

sltu $t0, $t1, $t2  # unsigned comparison

💡

Use for pointers and size_t-like logic.

slti

Comparison

Set on less than immediate (signed).

slti $t0, $t1, 10   # $t0 = 1 if $t1 < 10 (signed)

💡

Pairs with branch-on-true to emulate <=, >=, etc.

sltiu

Comparison

Set on less than immediate (unsigned).

sltiu $t0, $t1, 10  # unsigned compare with 10

💡

Great for bounds checks on indices.

and

Logic

Bitwise AND: rd = rs & rt.

and $t0, $t1, $t2   # mask bits

💡

Classic for clearing bits with a mask.

or

Logic

Bitwise OR: rd = rs | rt.

or $t0, $t1, $t2    # set bits

💡

Combine masks to assemble values.

xor

Logic

Bitwise XOR: rd = rs ^ rt.

xor $t0, $t1, $t2   # toggle bits

💡

Swap trick uses XOR, but be careful with aliasing.

nor

Logic

Bitwise NOR: rd = ~(rs | rt).

nor $t0, $t1, $t2   # bitwise NOT of OR

💡

Used to synthesize NOT: nor $t0, $t1, $zero.

andi

Logic

Bitwise AND immediate: rt = rs & imm (zero-extended).

andi $t0, $t1, 0xFF # keep low byte

💡

Immediate is zero-extended, not sign-extended.

ori

Logic

Bitwise OR immediate: rt = rs | imm (zero-extended).

ori $t0, $t1, 0x20   # set bit 5

💡

Common with LUI to build 32-bit constants.

xori

Logic

Bitwise XOR immediate: rt = rs ^ imm (zero-extended).

xori $t0, $t1, 1     # toggle LSB

💡

XOR with same value twice gets you back the original.

lui

Data Movement

Load upper immediate: rt = imm << 16.

lui $t0, 0x1234     # $t0 = 0x12340000

💡

Usually followed by ORI to form a full 32-bit constant.

sll

Shift

Logical left shift: rd = rt << shamt.

sll $t0, $t1, 2     # multiply by 4

💡

nop is sll $zero, $zero, 0.

srl

Shift

Logical right shift: rd = rt >>> shamt (zeros in).

srl $t0, $t1, 1     # divide by 2 (unsigned)

💡

Use sra for signed arithmetic right shift.

sra

Shift

Arithmetic right shift: rd = rt >> shamt (sign-ext).

sra $t0, $t1, 1     # divide by 2 (signed)

💡

Maintains sign for negative numbers.

sllv

Shift

Variable logical left shift: rd = rt << rs[4:0].

sllv $t0, $t1, $t2  # shift by $t2 amount

💡

Shift amount comes from a register instead of shamt.

srlv

Shift

Variable logical right shift: rd = rt >>> rs[4:0].

srlv $t0, $t1, $t2  # variable shift right (zeros)

💡

Great for bitfield extraction.

srav

Shift

Variable arithmetic right shift: rd = rt >> rs[4:0].

srav $t0, $t1, $t2  # variable signed shift right

💡

Preserves sign across variable shifts.

mult

Multiply/Divide

Signed multiply: HI|LO = rs * rt (low 32 in LO, high 32 in HI).

mult $t1, $t2  
mflo $t0        # $t0 = low 32 bits

💡

Use mfhi/mflo to read the results; operation is 64-bit internally.

multu

Multiply/Divide

Unsigned multiply: HI|LO = rs * rt (unsigned).

multu $t1, $t2 
mfhi $t3        # $t3 = high 32 bits

💡

Unsigned variant for size_t-like math.

div

Multiply/Divide

Signed divide: LO = rs / rt, HI = rs % rt.

div $t1, $t2 
mflo $t0  # quotient
mfhi $t3  # remainder

💡

Division by zero is undefined—don’t do it.

divu

Multiply/Divide

Unsigned divide: LO = rs / rt, HI = rs % rt (unsigned).

divu $t1, $t2 
mflo $t0 
mfhi $t3

💡

Match your data types when choosing div vs divu.

mfhi

HI/LO

Move From HI: rd = HI.

mfhi $t0  # get remainder or high product

💡

Pairs with mult*/div* to harvest high 32 bits.

mflo

HI/LO

Move From LO: rd = LO.

mflo $t0  # get quotient or low product

💡

You typically read LO first after mult/div.

mthi

HI/LO

Move To HI: HI = rs.

mthi $t0  # set HI explicitly

💡

Less common; can seed HI/LO for custom arithmetic.

mtlo

HI/LO

Move To LO: LO = rs.

mtlo $t0  # set LO explicitly

💡

Caution: overwrites results from mult/div.

j

Control Flow

Jump to absolute target in same 256 MB region.

j main    # PC = target

💡

Assembler fills the 26-bit target field.

jal

Control Flow

Jump and link: $ra = return addr; jump to target.

jal func  # call func; $ra = next PC

💡

Your automatic ‘bookmark’ to get home from a call.

jr

Control Flow

Jump register: PC = rs (return or indirect jump).

jr $ra    # return to caller

💡

Commonly used to return from subroutines.

jalr

Control Flow

Jump and link register: rd=$ra (default), PC=rs.

jalr $t0        # call via pointer in $t0

💡

Useful for function pointers / virtual dispatch.

beq

Control Flow

Branch if equal: if (rs == rt) PC += offset.

beq $t0, $t1, loop   # if equal, branch

💡

Offset is word-aligned relative to the delay slot.

bne

Control Flow

Branch if not equal: if (rs != rt) PC += offset.

bne $t0, $t1, loop   # if not equal, branch

💡

Classic for while/for loops.

blez

Control Flow

Branch if less than or equal to zero (signed).

blez $t0, done  # if $t0 <= 0

💡

One-source-operand branch; compares to zero.

bgtz

Control Flow

Branch if greater than zero (signed).

bgtz $t0, loop  # if $t0 > 0

💡

Complements blez/bltz/bgez.

bltz

Control Flow

Branch if less than zero (signed).

bltz $t0, neg   # if $t0 < 0

💡

Implemented via the REGIMM encoding group.

bgez

Control Flow

Branch if greater than or equal to zero (signed).

bgez $t0, nonneg # if $t0 >= 0

💡

Pairs with bltz for signed zero tests.

bltzal

Control Flow

Branch if < 0 and link (like call-if-negative).

bltzal $t0, handler  # if negative, $ra=ret; jump

💡

Useful for conditional calls / trampolines.

bgezal

Control Flow

Branch if >= 0 and link.

bgezal $t0, handler  # if nonnegative, call handler

💡

Dual of bltzal for nonnegative case.

lb

Memory

Load byte (signed): rt = sign_extend(M8[rs + imm]).

lb $t0, 0($t1)   # signed 8-bit load

💡

Sign-extends bit 7 into upper bits.

lbu

Memory

Load byte (unsigned): rt = zero_extend(M8[rs + imm]).

lbu $t0, 0($t1)  # unsigned 8-bit

💡

Great for ASCII/bytes processing.

lh

Memory

Load halfword (signed): rt = sign_extend(M16[rs + imm]).

lh $t0, 0($t1)   # signed 16-bit load (aligned)

💡

Requires halfword alignment on MIPS I.

lhu

Memory

Load halfword (unsigned): rt = zero_extend(M16[rs + imm]).

lhu $t0, 0($t1)  # unsigned 16-bit load

💡

Keeps upper bits zero.

lw

Memory

Load word: rt = M32[rs + imm].

lw $t0, 4($sp)   # load 32-bit word

💡

Requires word alignment on MIPS I.

sb

Memory

Store byte: M8[rs + imm] = rt[7:0].

sb $t0, 0($t1)   # store low byte

💡

Upper 24 bits of rt are ignored.

sh

Memory

Store halfword: M16[rs + imm] = rt[15:0].

sh $t0, 2($t1)   # store 16 bits (aligned)

💡

Requires halfword alignment.

sw

Memory

Store word: M32[rs + imm] = rt.

sw $t0, 8($sp)   # store 32-bit word

💡

Workhorse for saving registers on stack.

lui (as const-build)

Data Movement

First half of building 32-bit constants (upper 16 bits).

lui $t0, 0x1234 
ori $t0, $t0, 0x5678

💡

MIPS lacks a single ‘load 32-bit immediate’ real instruction.

syscall

System

Enter operating system / simulator service routine.

li $v0, 1
li $a0, 42
syscall   # print_int in SPIM/MARS

💡

Meaning depends on $v0 in simulators like MARS/QtSPIM.

break

System

Breakpoint exception for debuggers.

break 0        # trigger BREAK exception

💡

Handy for trapping illegal states while debugging.

move

Pseudoinstruction

Copy register (pseudo): rd = rs.

move $t0, $t1     # expands to addu $t0,$t1,$zero

💡

Just OR/ADDU with $zero under the hood.

li

Pseudoinstruction

Load immediate (pseudo): rt = imm (32-bit).

li $t0, 0x12345678  # expands to LUI/ORI pair

💡

Short immediates may expand to a single addiu/ori.

la

Pseudoinstruction

Load address (pseudo): rt = address(label).

la $t0, array     # builds absolute address

💡

Assembles using LUI/ORI (and possibly relocation).

neg

Pseudoinstruction

Negate (pseudo): rd = -rs.

neg $t0, $t1      # expands to subu $t0,$zero,$t1

💡

Also exists as ‘negu’ pseudo for no-trap form.

not

Pseudoinstruction

Bitwise NOT (pseudo): rd = ~rs.

not $t0, $t1      # expands to nor $t0,$t1,$zero

💡

Uses NOR trick to invert bits.

nop

Pseudoinstruction

No operation (pseudo): does nothing.

nop               # sll $zero,$zero,0

💡

Often used to fill delay slots in older pipelines.

b

Pseudoinstruction

Unconditional branch (pseudo).

b loop            # expands to beq $zero,$zero,loop

💡

Nice for simple gotos/loops.

bal

Pseudoinstruction

Branch and link (pseudo): like jal with PC-relative target.

bal func          # expands via bgezal $zero, func (tool-dependent)

💡

Assembler tricks vary; effect is set $ra and branch.

beqz

Pseudoinstruction

Branch if equal to zero (pseudo).

beqz $t0, done    # beq $t0,$zero,done

💡

Saves you a $zero in the mnemonic.

bnez

Pseudoinstruction

Branch if not equal to zero (pseudo).

bnez $t0, loop    # bne $t0,$zero,loop

💡

Common in while loops.

ble

Pseudoinstruction

Branch if ≤ (pseudo, signed).

ble $t0, $t1, L   # expands via slt/bne patterns

💡

Assembler synthesizes using slt/beq/bne sequences.

bge

Pseudoinstruction

Branch if ≥ (pseudo, signed).

bge $t0, $t1, L   # expands via slt/bne patterns

💡

No native ‘bge’ in MIPS I.

blt

Pseudoinstruction

Branch if < (pseudo, signed).

blt $t0, $t1, L   # expands via slt/bne

💡

Assembled with slt/beq combos.

bgt

Pseudoinstruction

Branch if > (pseudo, signed).

bgt $t0, $t1, L   # expands via slt/bne

💡

Assembler sugar only.

seq

Pseudoinstruction

Set if equal (pseudo): rd = (rs == rt).

seq $t0, $t1, $t2  # expands via xor/sltiu/xori

💡

A convenient booleanizer in MARS/QtSPIM.

sne

Pseudoinstruction

Set if not equal (pseudo): rd = (rs != rt).

sne $t0, $t1, $t2  # expands via seq/xori

💡

Pairs with seq to build conditionals.

sle

Pseudoinstruction

Set if ≤ (pseudo, signed).

sle $t0, $t1, $t2  # pseudo via slt/seq/or

💡

Not a real opcode; assembler composes it.

sge

Pseudoinstruction

Set if ≥ (pseudo, signed).

sge $t0, $t1, $t2  # pseudo via slt/xori

💡

Assembler sugar for comparisons.

rol

Pseudoinstruction

Rotate left (pseudo).

rol $t0, $t1, 8    # pseudo via sll/srl/or

💡

No real rotate in MIPS I—built from shifts.

ror

Pseudoinstruction

Rotate right (pseudo).

ror $t0, $t1, 8    # pseudo via srl/sll/or

💡

Assembler expands with opposite shifts and OR.

MIPS Learn

MIPS Dictionary

add

addu

sub

subu

addi

addiu

slt

sltu

slti

sltiu

and

or

xor

nor

andi

ori

xori

lui

sll

srl

sra

sllv

srlv

srav

mult

multu

div

divu

mfhi

mflo

mthi

mtlo

j

jal

jr

jalr

beq

bne

blez

bgtz

bltz

bgez

bltzal

bgezal

lb

lbu

lh

lhu

lw

sb

sh

sw

lui (as const-build)

syscall

break

move

li

la

neg

not

nop

b

bal

beqz

bnez

ble

bge

blt

bgt

seq

sne

sle

sge

rol

ror

MIPS Learn

MIPS Dictionary

add